1. Field
The present embodiments relate to storage devices for computer systems. More specifically, the present embodiments relate to techniques for simultaneously transferring data from the devices and performing error control on the data to reduce latency and improve throughput to a host.
2. Related Art
A modern computer system typically includes a motherboard containing a processor and memory, along with a set of peripheral components connected to the motherboard via a variety of interfaces. For example, a Serial Advanced Technology Attachment (SATA) interface may facilitate data transfer between a storage device (e.g., hard disk drive, optical drive, solid-state drive, hybrid hard drive, etc.) and the motherboard, while a Peripheral Component Interconnect Express (PCIe) bus may enable communication between the motherboard and a number of integrated and/or add-on peripheral components.
In addition, the throughputs and/or latencies of the interfaces may affect the rates at which data is transferred between components in computer systems. For example, a SATA interface may enable the serial transfer of data between a storage device and a motherboard at rates of up to 6 Gbits/s. Prior to transmission of the data over the SATA interface, error detection and/or correction may be performed on the data, thus increasing the latency of the data transmission. Also, 8 b/10 b encoding of the transmitted data may cause additional overhead. As a result, the SATA interface may provide an effective throughput of approximately 550 MB/s.
At the same time, devices connected to the interfaces are operating at progressively faster speeds. For example, a solid-state drive (SSD) may implement data striping and/or interleaving on multiple flash chips. In turn, read/write operations on the SSD may be performed in parallel on the flash chips, providing effective read/write speeds of over 700 MB/s on the SSDs. Consequently, data transfer between high-speed components in computer systems may be increasingly limited by the signaling capabilities of interfaces connecting the components.
Hence, what is needed is a mechanism for reducing the latencies and/or increasing the throughputs of interfaces between components in computer systems.